diff -rNau uClinux-evm50100/linux-2.4.x/drivers/char/serial_samsung.c uClinux-evm4530/linux-2.4.x/drivers/char/serial_samsung.c --- uClinux-evm50100/linux-2.4.x/drivers/char/serial_samsung.c Tue Mar 5 17:14:11 2002 +++ uClinux-evm4530/linux-2.4.x/drivers/char/serial_samsung.c Mon Oct 20 17:07:09 2003 @@ -543,7 +543,29 @@ unsigned char ch; struct async_icount *icount; int max_count = 256; - + + int uart_sr_oe; // Overrun error + int uart_sr_pe; // Parity error + int uart_sr_fe; // Frame error + int uart_sr_bi; // Break detect + int uart_sr_dr; + int uart_sr; + + if( (CSR_READ(SYSCFG) & SYSCFG_4530) != SYSCFG_4530 ) { + uart_sr_oe = UART_4510_LSR_OE; + uart_sr_pe = UART_4510_LSR_PE; + uart_sr_fe = UART_4510_LSR_FE; + uart_sr_bi = UART_4510_LSR_BI; + uart_sr = UART_4510_LSR; + uart_sr_dr = UART_4510_LSR_DR; /* data ready */ + } else { + uart_sr_oe = UART_4530_SR_OER; /* rx overrun error */ + uart_sr_pe = UART_4530_SR_PER; /* rx parity error */ + uart_sr_fe = UART_4530_SR_FER; /* rx frame error */ + uart_sr_bi = UART_4530_SR_BSD; /* break signal detected */ + uart_sr = UART_4530_SR; + uart_sr_dr = UART_4530_SR_RDV; + } #ifdef CONFIG_LEDMAN ledman_cmd(LEDMAN_CMD_SET, (info->line == 0) ? LEDMAN_COM1_RX : LEDMAN_COM2_RX); @@ -564,13 +586,13 @@ printk("DR%02x:%02x...", ch, *status); #endif *tty->flip.flag_buf_ptr = 0; - if (*status & (UART_LSR_BI | UART_LSR_PE | - UART_LSR_FE | UART_LSR_OE)) { + if (*status & (uart_sr_bi | uart_sr_pe | + uart_sr_fe | uart_sr_oe)) { // // For statistics only // - if (*status & UART_LSR_BI) { - *status &= ~(UART_LSR_FE | UART_LSR_PE); + if (*status & uart_sr_bi) { + *status &= ~(uart_sr_fe | uart_sr_pe); icount->brk++; // // We do the SysRQ and SAK checking @@ -589,11 +611,11 @@ #endif if (info->flags & ASYNC_SAK) do_SAK(tty); - } else if (*status & UART_LSR_PE) + } else if (*status & uart_sr_pe) icount->parity++; - else if (*status & UART_LSR_FE) + else if (*status & uart_sr_fe) icount->frame++; - if (*status & UART_LSR_OE) + if (*status & uart_sr_oe) icount->overrun++; // @@ -608,14 +630,14 @@ lsr_break_flag = 0; } #endif - if (*status & (UART_LSR_BI)) { + if (*status & (uart_sr_bi)) { #ifdef SERIAL_DEBUG_INTR printk("handling break...."); #endif *tty->flip.flag_buf_ptr = TTY_BREAK; - } else if (*status & UART_LSR_PE) + } else if (*status & uart_sr_pe) *tty->flip.flag_buf_ptr = TTY_PARITY; - else if (*status & UART_LSR_FE) + else if (*status & uart_sr_fe) *tty->flip.flag_buf_ptr = TTY_FRAME; } #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) @@ -634,7 +656,7 @@ tty->flip.char_buf_ptr++; tty->flip.count++; } - if ((*status & UART_LSR_OE) && + if ((*status & uart_sr_oe) && (tty->flip.count < TTY_FLIPBUF_SIZE)) { // // Overrun is special, since it's reported @@ -649,8 +671,8 @@ #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) ignore_char: #endif - *status = serial_inp(info, UART_LSR); - } while ((*status & UART_LSR_DR) && (max_count-- > 0)); + *status = serial_inp(info, uart_sr); + } while ((*status & uart_sr_dr) && (max_count-- > 0)); #if (LINUX_VERSION_CODE > 131394) // 2.1.66 tty_flip_buffer_push(tty); #else @@ -877,7 +899,18 @@ int first_multi = 0; struct rs_multiport_struct *multi; #endif - + int uart_sr; + int uart_sr_dr; + int uart_sr_thre; + if( (CSR_READ(SYSCFG) & SYSCFG_4530) != SYSCFG_4530 ) { + uart_sr = UART_4510_LSR; + uart_sr_dr = UART_4510_LSR_DR; + uart_sr_thre = UART_4510_LSR_THRE; + } else { + uart_sr = UART_4530_SR; + uart_sr_dr = UART_4530_SR_RDV; + uart_sr_thre = UART_4530_SR_THE; + } #ifdef SERIAL_DEBUG_INTR printk("rs_interrupt_single(%d)...", irq); #endif @@ -893,15 +926,15 @@ #endif do { - status = serial_inp(info, UART_LSR); + status = serial_inp(info, uart_sr); #ifdef SERIAL_DEBUG_INTR printk("status = %x...", status); #endif - if (status & UART_LSR_DR) + if (status & uart_sr_dr) receive_chars(info, &status, regs); // 12/27/2001 Mac Wang Samsung 4510 doesn't have modem relate registers // check_modem_status(info); - if (status & UART_LSR_THRE) + if (status & uart_sr_thre) transmit_chars(info, 0); if (pass_counter++ > RS_ISR_PASS_LIMIT) { #if 0 @@ -912,7 +945,7 @@ #ifdef SERIAL_DEBUG_INTR printk("IIR = %x...", serial_in(info, UART_IIR)); #endif - } while (!(status & (UART_LSR_DR | UART_LSR_THRE))); + } while (!(status & (uart_sr_dr | uart_sr_thre))); // } while (!(serial_in(info, UART_IIR) & UART_IIR_NO_INT)); info->last_active = jiffies; #ifdef CONFIG_SERIAL_MULTIPORT @@ -1385,31 +1418,36 @@ IRQ_ports[state->irq - 1] = info; figure_IRQ_timeout(state->irq - 1); - // // Now, initialize the UART - // -/* - serial_outp(info, UART_LCR, UART_LCR_WLEN8); // reset DLAB - - info->MCR = 0; - if (info->tty->termios->c_cflag & CBAUD) - info->MCR = UART_MCR_DTR | UART_MCR_RTS; -#ifdef CONFIG_SERIAL_MANY_PORTS - if (info->flags & ASYNC_FOURPORT) { - if (state->irq == 0) - info->MCR |= UART_MCR_OUT1; - } else -#endif - { - if (state->irq != 0) - info->MCR |= UART_MCR_OUT2; + if( (CSR_READ(SYSCFG) & SYSCFG_4530) != SYSCFG_4530 ) { + serial_outp(info, UART_4510_LCR, UART_4510_LCR_WLEN8); + serial_outp(info, UART_4510_GCR, + UART_4510_GCR_RX_INT | + UART_4510_GCR_TX_INT | + UART_4510_GCR_RX_STAT_INT + ); + } else { + serial_outp(info, UART_4530_CR, + UART_4530_CR_TMODE_INTREQ | /* 01=interrupt request */ + UART_4530_CR_RMODE_INTREQ | /* 01 = interrupt request */ + UART_4530_CR_WL8 | /* 11 = 8 bits */ + UART_4530_CR_TFEN | /* [16] Transmit FIFO enable */ + UART_4530_CR_RFEN | /* [17] Receive FIFO enable */ + UART_4530_CR_TFRST | /* [18] Transmit FIFO reset */ + UART_4530_CR_RFRST | /* [19] Receive FIFO reset */ + UART_4530_CR_TFTL_8 | /* 11 = 8/32 */ + UART_4530_CR_RFTL_1 /* 00 = 1-byte vaild/32-byte */ + ); + + serial_outp(info, UART_4530_IEN, + UART_4530_IEN_RDVIE | /* receive data valid */ + UART_4530_IEN_BSDIE | /* break signal detected */ + UART_4530_IEN_FERIE | /* Frame Error interrupt enable */ + UART_4530_IEN_PERIE | /* Parity Error interrupt enable */ + UART_4530_IEN_OERIE | /* Overrun Error interrupt enable */ + UART_4530_IEN_THEIE /* Transmit Holding Register Empty interrupt enable */ + ); } - info->MCR |= ALPHA_KLUDGE_MCR; // Don't ask - serial_outp(info, UART_MCR, info->MCR); -*/ - serial_outp(info, UART_LCR, UART_LCR_WLEN8); - serial_outp(info, UART_GCR, UART_GCR_RX_INT|UART_GCR_TX_INT|UART_GCR_RX_STAT_INT); - // // Finally, enable interrupts // @@ -1673,10 +1711,16 @@ struct termios *old_termios) { int quot = 0, baud_base, baud; -// unsigned cflag, cval, fcr = 0; unsigned cflag, cval; int bits; unsigned long flags; + int uart_thre; /* tx hold reg empty */ + int uart_dr; /* rx data received */ + int uart_oe; + int uart_fe; + int uart_pe; + int uart_bi; + if (!info->tty || !info->tty->termios) return; @@ -1685,51 +1729,88 @@ return; // byte size and parity - switch (cflag & CSIZE) { - case CS5: cval = 0x00; bits = 7; break; - case CS6: cval = 0x01; bits = 8; break; - case CS7: cval = 0x02; bits = 9; break; - case CS8: cval = 0x03; bits = 10; break; - // Never happens, but GCC is too dumb to figure it out - default: cval = 0x00; bits = 7; break; - } - if (cflag & CSTOPB) { + cval = 0x00; + + if( (CSR_READ(SYSCFG) & SYSCFG_4530) != SYSCFG_4530 ) { + uart_thre = UART_4510_LSR_THRE; // Transmit buffer register empty + uart_dr = UART_4510_LSR_DR; // Receive data ready + uart_oe = UART_4510_LSR_OE; // Overrun error + uart_fe = UART_4510_LSR_FE; // Frame error + uart_pe = UART_4510_LSR_PE; // Parity error + uart_bi = UART_4510_LSR_BI; // Break detect + + /* c3c4510 */ + switch (cflag & CSIZE) { + case CS5: cval = 0x00; bits = 7; break; + case CS6: cval = 0x01; bits = 8; break; + case CS7: cval = 0x02; bits = 9; break; + case CS8: cval = 0x03; bits = 10; break; + // Never happens, but GCC is too dumb to figure it out + default: cval = 0x00; bits = 7; break; + } + + if (cflag & PARODD) + cval |= UART_4510_LCR_OPAR; + else if (cflag & PARENB) + cval |= UART_4510_LCR_EPAR; + else + cval |= UART_4510_LCR_NPAR; + + if (cflag & CSTOPB) { cval |= 0x04; bits++; - } - if (cflag & PARENB) { + } + if (cflag & PARENB) { bits++; - } - if (cflag & PARODD) - cval |= UART_LCR_OPAR; - else if (cflag & PARENB) - cval |= UART_LCR_EPAR; - else - cval |= UART_LCR_NPAR; -/* - if (cflag & PARENB) { - cval |= UART_LCR_PARITY; + } + + } else { + uart_thre = UART_4530_SR_THE; // Transmit buffer register empty + uart_dr = UART_4530_SR_RDV; // Receive data ready + uart_oe = UART_4530_SR_OER; // Overrun error + uart_fe = UART_4530_SR_FER; // Frame error + uart_pe = UART_4530_SR_PER; // Parity error + uart_bi = UART_4530_SR_BSD; // Break detect + + switch (cflag & CSIZE) { + case CS5: cval = UART_4530_CR_WL5; bits = 7; break; + case CS6: cval = UART_4530_CR_WL6; bits = 8; break; + case CS7: cval = UART_4530_CR_WL7; bits = 9; break; + case CS8: cval = UART_4530_CR_WL8; bits = 10; break; + // Never happens, but GCC is too dumb to figure it out + default: cval = UART_4530_CR_WL5; bits = 7; break; + } + + if (cflag & PARODD) + cval |= UART_4530_CR_ODD; + else if (cflag & PARENB) + cval |= UART_4530_CR_EVEN; + else + cval |= UART_4530_CR_NO; + + if (cflag & CSTOPB) { + cval |= UART_4530_CR_STOP_2; + bits++; + } + if (cflag & PARENB) { bits++; + } + cval |= + UART_4530_CR_TMODE_INTREQ | /* 01=interrupt request */ + UART_4530_CR_RMODE_INTREQ | /* 01 = interrupt request */ + UART_4530_CR_TFEN | /* [16] Transmit FIFO enable */ + UART_4530_CR_RFEN | /* [17] Receive FIFO enable */ + UART_4530_CR_TFRST | /* [18] Transmit FIFO reset */ + UART_4530_CR_RFRST | /* [19] Receive FIFO reset */ + UART_4530_CR_TFTL_8 | /* 11 = 8/32 */ + UART_4530_CR_RFTL_1; /* 00 = 1-byte vaild/32-byte */ } - if (!(cflag & PARODD)) - cval |= UART_LCR_EPAR; -#ifdef CMSPAR - if (cflag & CMSPAR) - cval |= UART_LCR_SPAR; -#endif -*/ + // Determine divisor based on baud rate baud = tty_get_baud_rate(info->tty); if (!baud) baud = 9600; // B0 transition handled in rs_set_termios -/* -#ifdef CONFIG_SERIAL_RSA - if ((info->state->type == PORT_RSA) && - (info->state->baud_base != SERIAL_RSA_BAUD_BASE) && - enable_rsa(info)) - info->state->baud_base = SERIAL_RSA_BAUD_BASE; -#endif -*/ + baud_base = info->state->baud_base; /* if (info->state->type == PORT_16C950) { @@ -1834,33 +1915,33 @@ // #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK)) - info->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; + info->read_status_mask = uart_oe | uart_thre | uart_dr; if (I_INPCK(info->tty)) - info->read_status_mask |= UART_LSR_FE | UART_LSR_PE; + info->read_status_mask |= uart_fe | uart_pe; if (I_BRKINT(info->tty) || I_PARMRK(info->tty)) - info->read_status_mask |= UART_LSR_BI; - + info->read_status_mask |= uart_bi; + // // Characters to ignore // info->ignore_status_mask = 0; if (I_IGNPAR(info->tty)) - info->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; + info->ignore_status_mask |= uart_pe | uart_fe; if (I_IGNBRK(info->tty)) { - info->ignore_status_mask |= UART_LSR_BI; + info->ignore_status_mask |= uart_bi; // // If we're ignore parity and break indicators, ignore // overruns too. (For real raw support). // if (I_IGNPAR(info->tty)) - info->ignore_status_mask |= UART_LSR_OE; + info->ignore_status_mask |= uart_oe; } #if 0 // breaks serial console during boot stage // // !!! ignore all characters if CREAD is not set // if ((cflag & CREAD) == 0) - info->ignore_status_mask |= UART_LSR_DR; + info->ignore_status_mask |= uart_dr; #endif save_flags(flags); cli(); /* @@ -1891,7 +1972,11 @@ } */ serial_outp(info, UART_BDR, baudrate_div(baud)); - serial_outp(info, UART_LCR, cval); + if( (CSR_READ(SYSCFG) & SYSCFG_4530) != SYSCFG_4530 ) { + serial_outp(info, UART_4510_LCR, cval); + } else { + serial_outp(info, UART_4530_CR, cval); + } restore_flags(flags); } @@ -2342,10 +2427,16 @@ unsigned long flags; save_flags(flags); cli(); - status = serial_in(info, UART_LSR); - restore_flags(flags); - result = ((status & UART_LSR_TEMT) ? TIOCSER_TEMT : 0); - + if( (CSR_READ(SYSCFG) & SYSCFG_4530) != SYSCFG_4530 ) { + status = serial_in(info, UART_4510_LSR); + restore_flags(flags); + result = ((status & UART_4510_LSR_TEMT) ? TIOCSER_TEMT : 0); + } else { + status = serial_in(info, UART_4530_SR); + restore_flags(flags); + result = ((status & UART_4530_SR_TC) ? TIOCSER_TEMT : 0); + /* ==== _TC ==== */ + } // // If we're about to load something into the transmit // register, we'll pretend the transmitter isn't empty to @@ -2514,11 +2605,20 @@ if (!CONFIGURED_SERIAL_PORT(info)) return; save_flags(flags); cli(); - if (break_state == -1) - info->LCR |= UART_LCR_SBC; - else - info->LCR &= ~UART_LCR_SBC; - serial_out(info, UART_LCR, info->LCR); + + if( (CSR_READ(SYSCFG) & SYSCFG_4530) != SYSCFG_4530 ) { + if (break_state == -1) + info->LCR |= UART_4510_LCR_SBC; + else + info->LCR &= ~UART_4510_LCR_SBC; + serial_out(info, UART_4510_LCR, info->LCR); + } else { + if (break_state == -1) + info->LCR |= UART_4530_CR_SBR; + else + info->LCR &= ~UART_4530_CR_SBR; + serial_out(info, UART_4530_CR, info->LCR); + } restore_flags(flags); } #endif @@ -2944,8 +3044,11 @@ // interrupt driver to stop checking the data ready bit in the // line status register. // - //info->IER &= ~UART_IER_RLSI; - info->read_status_mask &= ~UART_LSR_DR; + if( (CSR_READ(SYSCFG) & SYSCFG_4530) != SYSCFG_4530 ) { + info->read_status_mask &= ~UART_4510_LSR_DR; + } else { + info->read_status_mask &= ~UART_4530_SR_RDV; + } if (info->flags & ASYNC_INITIALIZED) { //serial_out(info, UART_IER, info->IER); enable_uart_rx_interrupt(info->line); @@ -2984,8 +3087,18 @@ { struct async_struct * info = (struct async_struct *)tty->driver_data; unsigned long orig_jiffies, char_time; + int uart_sr_temp; + int uart_sr; int lsr; - + + if( (CSR_READ(SYSCFG) & SYSCFG_4530) != SYSCFG_4530 ) { + uart_sr = UART_4510_LSR; + uart_sr_temp = UART_4510_LSR_TEMT; + } else { + uart_sr = UART_4530_SR; + uart_sr_temp = UART_4530_SR_THE; + } + if (serial_paranoia_check(info, tty->device, "rs_wait_until_sent")) return; @@ -3025,7 +3138,7 @@ printk("In rs_wait_until_sent(%d) check=%lu...", timeout, char_time); printk("jiff=%lu...", jiffies); #endif - while (!((lsr = serial_inp(info, UART_LSR)) & UART_LSR_TEMT)) { + while (!((lsr = serial_inp(info, uart_sr)) & uart_sr_temp)) { #ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT printk("lsr = %d (jiff=%lu)...", lsr, jiffies); #endif @@ -3036,6 +3149,7 @@ if (timeout && time_after(jiffies, orig_jiffies + timeout)) break; } + #ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT printk("lsr = %d (jiff=%lu)...done\n", lsr, jiffies); #endif @@ -3958,8 +4072,36 @@ UART_FCR_CLEAR_XMIT)); serial_outp(info, UART_FCR, 0); */ - serial_outp(info, UART_LCR, UART_LCR_WLEN8); - serial_outp(info, UART_GCR, UART_GCR_RX_INT|UART_GCR_TX_INT); + if( (CSR_READ(SYSCFG) & SYSCFG_4530) != SYSCFG_4530 ) { + serial_outp(info, UART_4510_LCR, UART_4510_LCR_WLEN8); + serial_outp(info, UART_4510_GCR, + UART_4510_GCR_RX_INT | + UART_4510_GCR_TX_INT | + UART_4510_GCR_RX_STAT_INT + ); + } else { + serial_outp(info, UART_4530_CR, + UART_4530_CR_TMODE_INTREQ | /* 01=interrupt request */ + UART_4530_CR_RMODE_INTREQ | /* 01 = interrupt request */ + UART_4530_CR_WL8 | /* 11 = 8 bits */ + UART_4530_CR_TFEN | /* [16] Transmit FIFO enable */ + UART_4530_CR_RFEN | /* [17] Receive FIFO enable */ + UART_4530_CR_TFRST | /* [18] Transmit FIFO reset */ + UART_4530_CR_RFRST | /* [19] Receive FIFO reset */ + UART_4530_CR_TFTL_8 | /* 11 = 8/32 */ + UART_4530_CR_RFTL_1 /* 00 = 1-byte vaild/32-byte */ + ); + + serial_outp(info, UART_4530_IEN, + UART_4530_IEN_RDVIE | /* receive data valid */ + UART_4530_IEN_BSDIE | /* break signal detected */ + UART_4530_IEN_FERIE | /* Frame Error interrupt enable */ + UART_4530_IEN_PERIE | /* Parity Error interrupt enable */ + UART_4530_IEN_OERIE | /* Overrun Error interrupt enable */ + UART_4530_IEN_THEIE /* Transmit Holding Register Empty interrupt enable */ + ); + } + (void)serial_in(info, UART_RX); // serial_outp(info, UART_IER, 0); @@ -4382,7 +4524,6 @@ */ #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE -#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) static struct async_struct async_sercons; @@ -4392,19 +4533,37 @@ static inline void wait_for_xmitr(struct async_struct *info) { unsigned int status, tmout = 1000000; + unsigned int uart_sr; + unsigned int uart_sr_bi; + unsigned int uart_mask; + if( (CSR_READ(SYSCFG) & SYSCFG_4530) != SYSCFG_4530 ) { + uart_sr = UART_4510_LSR; + uart_sr_bi = UART_4510_LSR_BI; + uart_mask = + UART_4510_LSR_THRE | + UART_4510_LSR_TEMT; + + } else { + uart_sr = UART_4530_SR; + uart_sr_bi = UART_4530_SR_BSD; + uart_mask = + UART_4530_SR_TC | /* transmit complete */ + UART_4530_SR_THE; /* transmit holding register empty */ + } do { - status = serial_in(info, UART_LSR); + status = serial_in(info, uart_sr); - if (status & UART_LSR_BI) - lsr_break_flag = UART_LSR_BI; + if (status & uart_sr_bi) + lsr_break_flag = uart_sr_bi; if (--tmout == 0) break; - } while((status & BOTH_EMPTY) != BOTH_EMPTY); + } while( (status & uart_mask) != uart_mask ); } + /* * Print a string to the serial port trying not to disturb * any possible real use of the port... @@ -4469,9 +4628,12 @@ //serial_out(info, UART_IER, 0x00); // disable_uart_rx_interrupt(info->line); - while ((serial_in(info, UART_LSR) & UART_LSR_DR) == 0); - c = serial_in(info, UART_RX); - + if( (CSR_READ(SYSCFG) & SYSCFG_4530) != SYSCFG_4530 ) { + while ((serial_in(info, UART_4510_LSR) & UART_4510_LSR_DR) == 0); + } else { + while ((serial_in(info, UART_4530_SR ) & UART_4530_SR_RDV) == 0); + } + c = serial_in(info, UART_RX); /* * Restore the interrupts */ @@ -4594,9 +4756,9 @@ #endif /* !__powerpc__ && !__alpha__ */ if (cflag & PARENB) { - cval |= UART_LCR_PARITY; - if (!(cflag & PARODD)) - cval |= UART_LCR_EPAR; +// cval |= UART_LCR_PARITY; === DDD +// if (!(cflag & PARODD)) === DDD +// cval |= UART_LCR_EPAR; === DDD } /* @@ -4619,7 +4781,7 @@ return -1; */ serial_out(info, UART_BDR, baudrate_div(baud)); - serial_out(info, UART_LCR, cval); +// serial_out(info, UART_LCR, cval); ==== DDD return 0; } diff -rNau uClinux-evm50100/linux-2.4.x/include/asm-armnommu/arch-samsung/hardware.h uClinux-evm4530/linux-2.4.x/include/asm-armnommu/arch-samsung/hardware.h --- uClinux-evm50100/linux-2.4.x/include/asm-armnommu/arch-samsung/hardware.h Sun Dec 22 21:26:29 2002 +++ uClinux-evm4530/linux-2.4.x/include/asm-armnommu/arch-samsung/hardware.h Mon Oct 20 08:36:51 2003 @@ -60,6 +60,8 @@ #define DRAMCON3 (Base_Addr+0x3038) #define REFEXTCON (Base_Addr+0x303C) +#define SYSCFG_4530 (0x0C000000) /* SYSCFG s3c4530 mask */ + /* *********************** */ /* Ethernet BDMA Registers */ /* *********************** */ @@ -163,6 +165,15 @@ #define UCON1 (Base_Addr+0xE004) #define USTAT0 (Base_Addr+0xD008) #define USTAT1 (Base_Addr+0xE008) +/* c3c4530 control registers */ +#define U_CON0 (Base_Addr+0xD000) /* c3c4530 UART0 control register */ +#define U_CON1 (Base_Addr+0xE000) /* c3c4530 UART1 control register */ +/* c3c4530 status regs */ +#define U_STAT0 (Base_Addr+0xD004) /* c3c4530 UART0 status register */ +#define U_STAT1 (Base_Addr+0xE004) /* c3c4530 UART1 status register */ +/* c3c4530 int enable regs */ +#define U_INTEN0 (Base_Addr+0xd008) /* c3c4530 UART0 interrupt enable register */ +#define U_INTEN1 (Base_Addr+0xe008) /* c3c4530 UART1 interrupt enable register */ #define UTXBUF0 (Base_Addr+0xD00C) #define UTXBUF1 (Base_Addr+0xE00C) #define URXBUF0 (Base_Addr+0xD010) @@ -178,23 +189,51 @@ #define DEBUG_RX_BUFF_BASE URXBUF0 #define DEBUG_UARTLCON_BASE ULCON0 #define DEBUG_UARTCONT_BASE UCON0 + #define DEBUG_U_CONT_BASE U_CON0 /* s3c4530 UART0 control register */ #define DEBUG_UARTBRD_BASE UBRDIV0 #define DEBUG_CHK_STAT_BASE USTAT0 + #define DEBUG_U_CHK_STAT_BASE U_STAT0 /* s3c4530 UART0 status register */ + #define DEBUG_U_INTEN_BASE U_INTEN0/* s3c4530 UART0 int enable register */ #elif DEBUG_CONSOLE == 1 #define DEBUG_TX_BUFF_BASE UTXBUF1 #define DEBUG_RX_BUFF_BASE URXBUF1 #define DEBUG_UARTLCON_BASE ULCON1 #define DEBUG_UARTCONT_BASE UCON1 + #define DEBUG_U_CONT_BASE U_CON1 /* s3c4530 UART1 control register */ #define DEBUG_UARTBRD_BASE UBRDIV1 - #define DEBUG_CHK_STAT_BASE USTAT1 + #define DEBUG_CHK_STAT_BASE USTAT1 + #define DEBUG_U_CHK_STAT_BASE U_STAT1 /* s3c4530 UART1 status register */ + #define DEBUG_U_INTEN_BASE U_INTEN1/* s3c4530 UART1 int enable register */ #endif + #define DEBUG_ULCON_REG_VAL (0x3) -#define DEBUG_UCON_REG_VAL (0x9) -#define DEBUG_UBRDIV_REG_VAL (0x500) -#define DEBUG_RX_CHECK_BIT (0X20) -#define DEBUG_TX_CAN_CHECK_BIT (0X40) -#define DEBUG_TX_DONE_CHECK_BIT (0X80) +#define DEBUG_UCON_REG_VAL (0x9) +/* s3c4530 control register */ +#define DEBUG_U_CON_REG_VAL ( \ + 0x00000001 /* tx mode = interrupt request */ |\ + 0x00000004 /* rx mode = interrupt request */ |\ + 0x00003000 /* word len = 8 bits */ |\ + 0x00010000 /* Transmit FIFO enable */ |\ + 0x00020000 /* Receive FIFO enable */ |\ + 0x00040000 /* Transmit FIFO reset */ |\ + 0x00080000 /* Receive FIFO reset */ |\ + 0x00300000 /* tx fifo level 11 = 8/32 */ |\ + 0x00000000 /* rx fifo level 00 = 1-byte vaild/32-byte*/ \ +) + +#define DEBUG_U_INTEN_REG_VAL ( \ + 0x00000001 /* Enable UART1 Rx Interrupt */ |\ + 0x00040000 /* enable transmit holding reg empty */ \ +) +#define DEBUG_UBRDIV_REG_VAL (0x500) +#define DEBUG_RX_CHECK_BIT (0X20) +#define DEBUG_TX_CAN_CHECK_BIT (0X40) /* tx buffer empty */ +#define DEBUG_TX_DONE_CHECK_BIT (0X80) /* transmit complete */ + +#define DEBUG_U_RX_CHECK_BIT (0x00000001) /* rx data */ +#define DEBUG_U_TX_CAN_CHECK_BIT (0x00040000) /* transmit holding register empty */ +#define DEBUG_U_TX_DONE_CHECK_BIT (0x00020000) /* transmit complete */ /* **************** */ diff -rNau uClinux-evm50100/linux-2.4.x/include/asm-armnommu/arch-samsung/serial.h uClinux-evm4530/linux-2.4.x/include/asm-armnommu/arch-samsung/serial.h --- uClinux-evm50100/linux-2.4.x/include/asm-armnommu/arch-samsung/serial.h Tue Mar 5 14:15:39 2002 +++ uClinux-evm4530/linux-2.4.x/include/asm-armnommu/arch-samsung/serial.h Mon Oct 20 16:49:09 2003 @@ -2,6 +2,7 @@ * linux/include/asm/arch-samsung/serial.h * 2001 Mac Wang */ + #ifndef __ASM_ARCH_SERIAL_H #define __ASM_ARCH_SERIAL_H @@ -17,36 +18,104 @@ { 0, BASE_BAUD, UART_BASE1, INT_UARTRX1, STD_COM_FLAGS }, /* ttyS1 */ #define EXTRA_SERIAL_PORT_DEFNS -#define UART_LCR 0x00 /* Line Control Register */ -#define UART_GCR 0x04 /* Global Control Register */ -#define UART_LSR 0x08 /* Line Status Reigster */ -#define UART_TX 0x0C /* TX buffer Register */ -#define UART_RX 0x10 /* RX buffer Register */ -#define UART_BDR 0x14 /* Baudrate Divisor Reigster */ - -#define UART_LSR_OE 0x01 // Overrun error -#define UART_LSR_PE 0x02 // Parity error -#define UART_LSR_FE 0x04 // Frame error -#define UART_LSR_BI 0x08 // Break detect -#define UART_LSR_DTR 0x10 // Data terminal ready -#define UART_LSR_DR 0x20 // Receive data ready -#define UART_LSR_THRE 0x40 // Transmit buffer register empty -#define UART_LSR_TEMT 0x80 // Transmit complete - -#define UART_LCR_WLEN5 0x00 -#define UART_LCR_WLEN6 0x01 -#define UART_LCR_WLEN7 0x02 -#define UART_LCR_WLEN8 0x03 -#define UART_LCR_PARITY 0x20 -#define UART_LCR_NPAR 0x00 -#define UART_LCR_OPAR 0x20 -#define UART_LCR_EPAR 0x28 -#define UART_LCR_SPAR -#define UART_LCR_SBC 0x40 - -#define UART_GCR_RX_INT 0x01 -#define UART_GCR_TX_INT 0x08 -#define UART_GCR_RX_STAT_INT 0x04 +#define UART_4510_LCR 0x00 /* Line Control Register */ +#define UART_4510_GCR 0x04 /* Global Control Register */ +#define UART_4510_LSR 0x08 /* Line Status Reigster */ +#define UART_4530_CR 0x00 /* s3c4530 UART control regisger */ +#define UART_4530_SR 0x04 /* s3c4530 UART status register */ +#define UART_4530_IEN 0x08 /* s3c4530 UART int enable register */ + +#define UART_TX 0x0C /* TX buffer Register */ +#define UART_RX 0x10 /* RX buffer Register */ +#define UART_BDR 0x14 /* Baudrate Divisor Reigster */ + + +#define UART_4510_LSR_OE 0x01 // Overrun error +#define UART_4510_LSR_PE 0x02 // Parity error +#define UART_4510_LSR_FE 0x04 // Frame error +#define UART_4510_LSR_BI 0x08 // Break detect +//#define UART_4510_LSR_DTR 0x10 // Data terminal ready +#define UART_4510_LSR_DR 0x20 // Receive data ready +#define UART_4510_LSR_THRE 0x40 // Transmit buffer register empty +#define UART_4510_LSR_TEMT 0x80 // Transmit complete + +#define UART_4510_LCR_WLEN5 0x00 +#define UART_4510_LCR_WLEN6 0x01 +#define UART_4510_LCR_WLEN7 0x02 +#define UART_4510_LCR_WLEN8 0x03 +#define UART_4510_LCR_PARITY 0x20 +#define UART_4510_LCR_NPAR 0x00 +#define UART_4510_LCR_OPAR 0x20 +#define UART_4510_LCR_EPAR 0x28 +#define UART_4510_LCR_SPAR +#define UART_4510_LCR_SBC 0x40 + +#define UART_4510_GCR_RX_INT 0x01 +#define UART_4510_GCR_TX_INT 0x08 +#define UART_4510_GCR_RX_STAT_INT 0x04 + +/* s3c4530 UART control regisger */ +#define UART_4530_CR_TMODE_INTREQ 0x00000001 /* 01=interrupt request */ +#define UART_4530_CR_RMODE_INTREQ 0x00000004 /* 01 = interrupt request */ +#define UART_4530_CR_SBR 0x00000010 /* [4] Send break */ + +#define UART_4530_CR_WL5 0x00000000 /* 00 = 5 bits */ +#define UART_4530_CR_WL6 0x00001000 /* 01 = 6 bits */ +#define UART_4530_CR_WL7 0x00002000 /* 10 = 7 bits */ +#define UART_4530_CR_WL8 0x00003000 /* 11 = 8 bits */ +#define UART_4530_CR_WL 0x00003000 /* [13:12] Word Length mask */ + +#define UART_4530_CR_TFEN 0x00010000 /* [16] Transmit FIFO enable */ +#define UART_4530_CR_RFEN 0x00020000 /* [17] Receive FIFO enable */ +#define UART_4530_CR_TFRST 0x00040000 /* [18] Transmit FIFO reset */ +#define UART_4530_CR_RFRST 0x00080000 /* [19] Receive FIFO reset */ +#define UART_4530_CR_TFTL_8 0x00300000 /* 11 = 8/32 */ +#define UART_4530_CR_RFTL_1 0x00000000 /* 00 = 1-byte vaild/32-byte */ + +#define UART_4530_CR_NO 0x00000000 /* 0xx = no parity */ +#define UART_4530_CR_ODD 0x00000400 /* 100 = odd parity */ +#define UART_4530_CR_EVEN 0x00000500 /* 101 = even parity */ +#define UART_4530_CR_CHK1 0x00000600 /* 110 = parity is forced,checked as a 1 */ +#define UART_4530_CR_CHK0 0x00000700 /* 111 = parity is forced,checked as a 0 */ +#define UART_4530_CR_PMD 0x00000700 /* parity mode mask */ +#define UART_4530_CR_STOP_2 0x00000800 /* two stop bit per frame */ + +/* s3c4530 UART status register */ +#define UART_4530_SR_RDV 0x00000001 /* rx data */ +#define UART_4530_SR_BSD 0x00000002 /* break signal detected */ +#define UART_4530_SR_FER 0x00000004 /* rx frame error */ +#define UART_4530_SR_PER 0x00000008 /* rx parity error */ +#define UART_4530_SR_OER 0x00000010 /* rx overrun error */ +#define UART_4530_SR_CCD 0x00000020 /* control character detected */ +#define UART_4530_SR_DCD 0x00000040 /* data carrier detect */ +#define UART_4530_SR_RFREA 0x00000080 /* rx fifo trigger level reached */ +#define UART_4530_SR_RFEMT 0x00000100 /* receive FIFO empty */ +#define UART_4530_SR_RFFUL 0x00000200 /* receive FIFO full */ +#define UART_4530_SR_RFOV 0x00000400 /* receive FIFO overrun */ +#define UART_4530_SR_RIDLE 0x00000800 /* receiver in idle */ +#define UART_4530_SR_E_RxTO 0x00001000 +#define UART_4530_SR_DSR 0x00004000 /* DSR */ +#define UART_4530_SR_CTS 0x00008000 /* STS */ +#define UART_4530_SR_E_CTS 0x00010000 /* E_CTS */ +#define UART_4530_SR_TC 0x00020000 /* transmit complete */ +#define UART_4530_SR_THE 0x00040000 /* transmit holding register empty */ +#define UART_4530_SR_TFEMT 0x00080000 /* */ +#define UART_4530_SR_TFFUL 0x00100000 + +/* s3c4530 interrupt enable register */ +#define UART_4530_IEN_RDVIE 0x00000001 /* receive data valid */ +#define UART_4530_IEN_BSDIE 0x00000002 /* break signal detected */ +#define UART_4530_IEN_FERIE 0x00000004 /* Frame Error interrupt enable */ +#define UART_4530_IEN_PERIE 0x00000008 /* Parity Error interrupt enable */ + #define UART_4530_IEN_OERIE 0x00000010 /* Overrun Error interrupt enable */ +#define UART_4530_IEN_CCDIE 0x00000020 /* Control Character Detect interrupt enable */ +#define UART_4530_IEN_DCDLIE 0x00000040 /* DCD High at receiver checking time interrupt enable */ +#define UART_4530_IEN_RFREAIE 0x00000080 /* Receive FIFO Data trigger level reach interrupt enable */ +#define UART_4530_IEN_OVFFIE 0x00000400 /* Receive FIFO overrun interrupt enable */ +#define UART_4530_IEN_E_RxTOIE 0x00001000 /* Receive Event time out interrupt enable */ +#define UART_4530_IEN_E_CTSIE 0x00010000 /* Event occurred interrupt enable */ +#define UART_4530_IEN_THEIE 0x00040000 /* Transmit Holding Register Empty interrupt enable */ + #define UART_MSR 0 #define UART_MSR_DCD 0 diff -rNau uClinux-evm50100/linux-2.4.x/include/asm-armnommu/arch-samsung/uncompress.c uClinux-evm4530/linux-2.4.x/include/asm-armnommu/arch-samsung/uncompress.c --- uClinux-evm50100/linux-2.4.x/include/asm-armnommu/arch-samsung/uncompress.c Tue Mar 5 12:39:26 2002 +++ uClinux-evm4530/linux-2.4.x/include/asm-armnommu/arch-samsung/uncompress.c Mon Oct 20 08:23:58 2003 @@ -3,20 +3,35 @@ * 2001 Mac Wang */ +/* + 2003 modified Dmitriy Cherkashin dch@ucrouter.ru +*/ + + #include static int s3c4510b_decomp_setup() { + CSR_WRITE(DEBUG_UARTBRD_BASE, DEBUG_UBRDIV_REG_VAL); + + if( (CSR_READ(SYSCFG) & SYSCFG_4530) != SYSCFG_4530) { CSR_WRITE(DEBUG_UARTLCON_BASE, DEBUG_ULCON_REG_VAL); CSR_WRITE(DEBUG_UARTCONT_BASE, DEBUG_UCON_REG_VAL); - CSR_WRITE(DEBUG_UARTBRD_BASE, DEBUG_UBRDIV_REG_VAL); + } else { + CSR_WRITE(DEBUG_U_CONT_BASE , DEBUG_U_CON_REG_VAL); + CSR_WRITE(DEBUG_U_INTEN_BASE , DEBUG_U_INTEN_REG_VAL); + } + } static int s3c4510b_putc(char c) { CSR_WRITE(DEBUG_TX_BUFF_BASE, c); - while(!(CSR_READ(DEBUG_CHK_STAT_BASE) & DEBUG_TX_DONE_CHECK_BIT)); - + if( (CSR_READ(SYSCFG) & SYSCFG_4530) != SYSCFG_4530) { + while(!(CSR_READ(DEBUG_CHK_STAT_BASE) & DEBUG_TX_DONE_CHECK_BIT)); + } else { + while(!(CSR_READ(DEBUG_U_CHK_STAT_BASE) & DEBUG_U_TX_DONE_CHECK_BIT)); + } if(c == '\n') s3c4510b_putc('\r'); }